`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/11/26 21:17:29
// Design Name: 
// Module Name: rv_mem
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module rv_mem(
    input CLK,input RST,
    //EX-->MEM
    input [4:0] INST_TYPE,
    input [1:0] EX_THREAD_ID,
    input [4:0] EX_RD_INDEX,
    input [31:0] EX_RD_VALUE,

    //DMEM --> MEM
    input [31:0] DMEM_DOUT,
    
    //MEM --> WB
    output [1:0] MEM_THREAD_ID,
    output [4:0] MEM_RD_INDEX,
    output [31:0] MEM_RD_VALUE
    );

    regw #(.WIDTH(2))THREAD_ID_REG (CLK,RST,1'b1,EX_THREAD_ID,MEM_THREAD_ID);
    regw #(.WIDTH(5)) RD_INDEX  (CLK,RST,1'b1,EX_RD_INDEX,MEM_RD_INDEX);
    wire [31:0] mem_dout;
    assign mem_dout=(INST_TYPE==`INST_LOAD)?DMEM_DOUT:EX_RD_VALUE;
    regw #(.WIDTH(32)) RD_VALUE  (CLK,RST,1'b1,mem_dout,MEM_RD_VALUE);
endmodule
